IEEE

Escaping the Academic Sandbox: Realizing VPR Circuits on Xilinx Devices

Abstract: This paper presents a new, open-source method for FPGA CAD researchers to realize their techniques on real Xilinx devices. Specifically, we extend the Verilog-To-Routing (VTR) suite, which ...
Design-Reuse

Xilinx Verilog and vhdl IP Listing

The T-COR-30 FPGA IP core implements the algorithm of automatic tracking of objects in video and calculation of their pa-rameters for solving guidance and target designation tasks. The IP core ... The ...
Design-Reuse

Xilinx Verilog vs systemverilog IP Listing

The BitCsi2Rx IP is a receiver for camera sensor signals, to be used in an FPGA or ASIC. It receives camera signals in accordance with the MIPI CSI-2 and D-PHY specifications. BitCsi2Rx converts ...
IEEE

Simulation and analysis of 1024 point FFT using Axi-protocol and Xilinx IP core

Abstract: This paper focuses on the implementation of a 1024-point FFT. A 1024-point FFT is significant in various applications, including signal processing, image processing, and communications, ...
GitHub

Using Parmys For Xilinx-Like Architectures

@amin1377 @WhiteNinjaZ Please check if the workaround in the mentioned issue works. You should only add temp dir path to your command : ./run_vtr_flow PATH_TO_VERILOG_FILE.v PATH_TO_ARCH_FILE.xml ...
GitHub

How to generate a .XO RTL kernel using verilog codes together and connects to a HLS kernel

Thank you for the tutorial, we now have a project on the U280 FPGA board involving a kernel writing in HLS and a kernel writing in Verilog. I am not sure how to build the project with both a HLS ...
Frontiers

Design and FPGA Implementation of a Pseudo-random Number Generator Based on a Hopfield Neural Network Under Electromagnetic Radiation

When implementing a pseudo-random number generator (PRNG) for neural network chaos-based systems on FPGAs, chaotic degradation caused by numerical accuracy constraints can have a dramatic impact on ...
Hackaday

FIR Filters For Xilinx

Digital filters are always an interesting topic, and they are especially attractive with FPGAs. [Pabolo] has been working with them in a series of blog posts. The latest covers an 8th order FIR filter ...